1. Field of the Invention
The present invention relates to a memory data synthesizer which is applied to a display controller etc. for displaying arbitrary characters or patterns on the screen of a display unit.
2. Description of the Background Art
In general, characters, patterns or the like are displayed on the screen of a television to indicate channels or various operating states. FIG. 1 is a block diagram showing a conventional display controller of this type.
Referring to FIG. 1, horizontal and vertical synchronizing signals are inputted through a synchronizing signal input circuit 1, and supplied to an oscillation circuit 2 and an H-counter 3. The oscillation circuit 2 is reset for every horizontal synchronizing signal, to oscillate at a prescribed frequency. Oscillation output from the oscillation circuit 2 is supplied to a timing generator 4, which in turn produces timing signals required for operations of respective parts and outputs the same to the respective parts. The H-counter 3 is reset for every vertical synchronizing signal, to count the horizontal synchronizing signal. The count value of the H-counter 3 is supplied to a display position detecting circuit 5 for detecting display positions of characters or patterns to be displayed.
On the other hand, data and addresses for displaying desired characters or patterns are inputted through an input control circuit 6. An address control circuit 7 addresses a display control register 8 and a display data RAM 9 in accordance with the inputted addresses. The display control register 8 and the display data RAM 9 are arranged on the same address space with assignment of different addresses, whereby the inputted data are written in designated addresses of the display control register 8 and the display data RAM 9 through a data control circuit 10. Such data include character code data, color information data, display mode data, display position data and the like.
The display position detecting circuit 5 compares display position data stored in the display control register 8 with the count value of the H-counter 3, and supplies a coincidence signal to a read address control circuit 11 when the data coincide with the count value. Thus, the read address control circuit 11 is activated to address the display data RAM 9, thereby to start reading of previously written data. The display data RAM 9 supplies addresses corresponding to previously written character code data to a character ROM 12, so that corresponding fonts are read from the character ROM 12 responsively.
Each font is formed by pixels of l.times.m dots, as shown in FIG. 11, for example. Assuming that the character ROM 12 stores such fonts for n characters, its capacity corresponds to l.times.m.times.n dots.
Data of the fonts read from the character ROM 12 are synthesized in a synthesizing circuit 13 at need. Output data from the synthesizing circuit 13 are converted from a parallel system into a serial system in a shift register 14, and supplied to a display control circuit 15. The display control circuit 15 receives color information data expressing character colors, background colors etc. from the display data RAM 9 and display mode data expressing character attribution etc. from the display control register 8 in addition to the font data from the shift register 14, to control the font data and the color information data in accordance with a display mode indicated by the display mode data. Thus, output signals of red, green and blue, a luminance control signal and the like are derived from the display control circuit 15, so that desired characters or patterns are displayed on the screen in accordance with these signals.
The character ROM 12 includes a read control circuit 16 and a ROM part 17 as shown in FIG. 2, for example. The read control circuit 16 is formed by an address decoder 18 and an output address circuit 19 as shown in FIG. 3, and the ROM part 17 is formed by m storage areas 17a to 17m as shown in FIG. 3, too. FIG. 4 shows the storage area 17b, for example, in detail. The remaining storage areas 17a and 17c to 17m are similar in structure. In this example, it is assumed that the character ROM 12 stores fonts of l.times.m dots for n characters.
Referring to FIG. 4, the storage area 17b includes l.times.n storage elements M.sub.11 to M.sub.ln, which are arranged in the form of a matrix. Each storage element is formed by an N-channel MOS transistor. The storage elements (M.sub.11 to M.sub.l1), (M.sub.12 to M.sub.l2), . . . , (M.sub.1n to M.sub.ln) in respective columns have gates which are commonly connected to word lines WL.sub.1, WL.sub.2, . . . , WL.sub.n, while the storage elements (M.sub.11 to M.sub.1n), (M.sub.21 to M.sub.2n), . . . , (M.sub.l1 to M.sub.ln) in respective rows have drains which are commonly guided to bit lines BL.sub.1, BL.sub.2, . . . , BL.sub.l. Only a storage element of a bit having data as a font has a drain connected to a corresponding bit line BL. Referring to FIG. 4, the drain of the storage element M.sub.31 is connected to the bit line BL.sub.3. This corresponds to writing of font data in a chequered position shown in FIG. 11. The word lines WL.sub.1 to WL.sub.n are commonly connected to all of the storage areas 17a to 17m.
The bit lines BL.sub.1 to BL.sub.l are connected to a power source through P-channel MOS transistors C.sub.1 to C.sub.l respectively. Data lines DL.sub.1 to DL.sub.m for the respective storage areas 17a to 17m are connected to a power source through P-channel MOS transistors E.sub.1 to E.sub.m respectively. At the beginning of every access, the timing generator 4 supplies a precharge signal PC to the gates of the P-channel MOS transistors C.sub.1 to C.sub.l and E.sub.1 to E.sub.m for a prescribed period, whereby the transistors C.sub.1 to C.sub.l and E.sub.1 to E.sub.m responsively conduct to precharge the bit lines BL.sub.1 to BL.sub.l and the data lines DL.sub.1 to DL.sub.m.
After such precharging, the address decoder 18 supplies one of address decode signals A.sub.1 to A.sub.n to a corresponding word line WL in response to an address from the display data RAM 9. Assuming that the address decode signal A.sub.1 is supplied to the word line WL.sub.1, for example, all of storage elements connected with the word line WL.sub.1 conduct. In the storage area 17b shown in FIG. 4, the storage elements M.sub.11 to M.sub.l1 conduct so that the charge precharged in the bit line BL.sub.3 is extracted through the storage element M.sub.31 which is connected to the bit line BL.sub.3.
The bit lines BL.sub.1 to BL.sub.l are commonly connected to the data line DL.sub.2 of the storage area 17b through output gate transistors G.sub.1 to G.sub.l which are formed by N-channel MOS transistors. The gates of the output gate transistors G.sub.1 to G.sub.l are connected to control lines CL.sub.1 to CL.sub.l respectively. The control lines CL.sub.1 to CL.sub.l are commonly connected with all of the storage areas 17a to 17m. The output address circuit 19 sequentially supplies signals B.sub.1 to B.sub.l to the control lines CL.sub.1 to CL.sub.l in response to a timing signal from the timing generator 4. In response to this, the output gate transistors G.sub.1 to G.sub.l sequentially conduct in the storage area 17b shown in FIG. 4, so that information in the bit lines BL.sub.1 to BL.sub.l is sequentially read on the data line DL.sub.2. Similar operation is simultaneously performed with respect to the remaining storage areas 17a and 17c to 17m, whereby m-bit data are read in parallel from the storage areas 17a to 17m on the data line DL.sub.1 to DL.sub.m. At the timing when a signal B.sub.3 is supplied to the control line CL.sub.3, for example, data on third bit lines BL.sub.3 of the storage areas 17a to 17m are read in parallel on the data lines DL.sub.1 to DL.sub.m. This corresponds to reading of m data on the third line in FIG. 11. Thus, in the conventional display controller of the above structure, one font is accessed upon every addressing.
It may be required for a display controller to synthesize a font 1 (FIG. 12A) and another font 2 (FIG. 12B) which are stored in the character ROM 12 with each other, in order to display a synthetic font shown in FIG. 12C on the screen in case of cursor display or underline display, for example. FIG. 5 is a timing chart of data reading in such case. Following a precharge signal PC, the display data RAM 9 supplies an address 1 to the address decoder 18, so that data on the corresponding font 1 is read from the ROM part 17 in response. Again following a precharge signal PC, the display data RAM 9 supplies an address 2 to the address decoder 18, so that data on the corresponding font 2 is read from the ROM part 17 in response. The data of the fonts 1 and 2 are supplied in parallel to the synthesizing circuit 13, which is formed by m RS flip-flops, which are arranged in parallel with each other, for example. The RS flip-flops are first set by the data of the font 1 and then set by the data of the font 2. The data of the fonts 1 and 2 are thus synthesized and latched. Thus, the synthetic font shown in FIG. 12C is produced.
In order to obtain a synthetic font in the conventional display controller, thus, it is necessary to access the character ROM 12 a plurality of times to synthesize respective outputs by the separately provided synthesizing circuit 13, thereby to obtain the logical sum and latch the same. In the display controller, on the other hand, characters or patterns must be outputted to a cathode ray tube or the like from the display control circuit 15, in response to scan timing of the television. Therefore, the data must be read from the character ROM 12 in real time with scanning, and hence high-speed access is required. However, it has been extremely difficult to access the character ROM 12 a plurality of times and synthesize the data read from the same in real time with scanning of the television.
It is wasteful and inefficient in circuit structure to provide a plurality of character ROMs 12 in order to obtain the synthetic output. It is also wasteful and inefficient in circuit structure to store synthetic fonts such as that shown in FIG. 12C in addition to normal fonts such as those shown in FIGS. 12A and 12B in the character ROM 12.